This disclosure relates to data processing and storage, and more specifically, to data storage systems, such as flash-based data storage systems, that selectively employ multiple data compression techniques.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.
Data storage systems, including those employing NAND flash media, commonly employ data compression to increase the effective storage capacity of a given storage system. In general, conventional data storage systems have implemented either hardware-based data compression or software-based data compression. Generally, software-based data compression techniques can achieve higher compression ratios (i.e., smaller data sets) at lower performance in terms of bandwidth and throughput, while hardware-based data compression techniques provide lower compression ratios (i.e., larger data sets) at higher performance in terms of bandwidth and throughput. Given these alternatives, data storage system designers have been forced to choose between high compression strength and high performance for the design of a given storage system.